The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for field effect transistors (FETs) including enhanced low-k spacer structures.
Semiconductor devices such as FETs, for example, typically include metal contacts to facilitate electrical conductivity with the gate regions and the source/drain (S/D) regions. The close proximity of the metal gate conductor to one or more of the S/D metal contacts can cause undesired parasitic capacitance. As the demand for semiconductor devices with reduced footprints continue, gate pitch dimensions are further reduced, which in turn increases the parasitic capacitance between the gate conductor and one or more of the S/D contacts.
FETs typically include a low-k dielectric spacer interposed between the gate conductor and the S/D contacts to mitigate the parasitic capacitance. Dielectric materials having low-dielectric constant (low-k) values can more effectively mitigate the parasitic capacitance. Conventional dielectric materials typically have a dielectric constant (k) ranging from about k=3 to about k=7.